product brief january 15, 2002 orca ? series 4 field-programmable gate arrays introduction built on the series 4 recon gurable embedded sys- tem-on-chip (soc) architecture, lattice introduces its new family of generic eld-programmable gate arrays (fpga). the high-performance and highly versatile architecture brings a new dimension to bringing net- wo rk system designs to market in less time than ever before. this new device family offers many new fea- tures and architectural enhancements not available in any earlier fpga generations. bringing together highly e xible sram-based programmable logic, powerful system features, a rich hierarchy of routing and interconnect resources, and meeting multiple interface standards, the series 4 fpga accommo- dates the most complex and high-performance intel- lectual property (ip) network designs. programmable features high-performance platform design: ? 0.16 m 7-level metal technology. ? internal performance of >250 mhz. ? i/o performance of >420 mhz. ? meets multiple i/o interface standards. ? 1.5 v operation (30% less power than 1.8 v operation) translates to greater performance. tr aditional i/o selections: ? lvttl and lvcmos (3.3 v, 2.5 v, and 1.8 v) i/os. ? per pin-selectable i/o clamping diodes provide 3.3 v pci compliance. ? individually programmable drive capability: 24 ma sink/12 ma source, 12 ma sink/6 ma source, or 6 ma sink/3 ma source. ? two slew rates supported (fast and slew-lim- ited). ? fast-capture input latch and input ip- op (ff)/latch for reduced input setup time and zero hold time. ? fast open-drain drive capability. ? capability to register 3-state enable signal. ? off-chip clock drive capability. ? two-input function generator in output path. new programmable high-speed i/o: ? single-ended: gtl, gtl+, pecl, sstl3/2 (class i and ii), hstl (class i, iii, and iv), zbt, and ddr. ? double-ended: ldvs, bused-lvds, and l vpecl. programmable (on/off) internal parallel termination (100 ? ) also supported for these i/os. tab le 1. orca series 4?available fpga logic * the usable gate counts range from a logic-only gate count to a gate count assuming 20% of the pfus/slics being used as rams. t he logic-only gate count includes each pfu/slic (counted as 108 gates/pfu), including 12 gates per lut/ff pair (eight per pfu) and 12 gates per slic/ff pair (one per pfu). each of the four pio groups are counted as 16 gates (three ffs, fast-capture latch, ou tput logic, clk, and i/o buffers). pfus used as ram are counted at four gates per bit, with each pfu capable of implementing a 32 x 4 ram (or 512 gates) per pfu. embedded block ram (ebr) is counted as four gates per bit, plus each block has an additional 25 k gates . 7 k gates are used for each pll and 50k gates for the embedded system bus and microprocessor interface logic. both the ebr and plls are conservatively utilized in the gate count calculations. note: devices are not pinout compatible with orca series 2/3. device rows columns pfus user i/o luts ebr blocks ebr bits (k) usable* gates (k) or4e2 26 24 624 400 4,992 8 74 260?515 or4e4 36 36 1296 576 10,368 12 111 380?800 or4e6 46 44 2024 720 16,192 16 147 515?1095
2 2 lattice semiconductor product brief january 15, 2002 field-programmable gate arrays orca series 4 programmable features (continued) new capability to (de)multiplex i/o signals: ? new double data rate on both input and output at r ates up to 350 mhz (700 mhz effective rate). ? new 2x and 4x downlink and uplink capability per i/o (i.e., 50 mhz internal to 200 mhz i/o). enhanced twin-quad programmable function unit (pfu): ? eight 16-bit look-up tables (luts) per pfu. ? nine user registers per pfu, one following each lut and organized to allow two nibbles to act independently, plus one extra for arithmetic opera- tions. ? new register control in each pfu has two inde- pendent programmable clocks, clock enables, local set/reset, and data selects. ? new lut structure allows e xible combinations of lut4, lut5, new lut6, 4 to 1 mux, new 8 to 1 mux, and ripple mode arithmetic functions in the same pfu. ? 32 x 4 ram per pfu, con gurable as single- or dual-port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the slic decoders as bank drivers. ? soft-wired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu through fast internal routing, which reduces rout- ing congestion and improves speed. ? flexible fast access to pfu inputs from routing. ? fast-carry logic and routing to all four adjacent pfus for nibble-, byte-wide, or longer arithmetic functions, with the option to register the pfu carry-out. abundant high-speed buffered and nonbuffered rout- ing resources provide 2x average speed improve- ments over previous architectures. hierarchical routing optimized for both local and glo- bal routing with dedicated routing resources. this results in faster routing times with predictable and ef cient performance. slic provides eight 3-statable buffers, up to 10-bit decoder, and pa l ?-like and-or-invert (aoi) in each programmable logic cell. improved built-in clock management with program- mable phase-locked loops (pplls) provide optimum clock modi cation and conditioning for phase, fre- quency, and duty cycle from 20 mhz up to 420 mhz. multiplication of the input frequency up to 64x, and division of the input frequency down to 1/64x, is pos- sible. new 200 mhz embedded quad-port ram blocks, two read ports, two write ports, and two sets of byte lane enables. each embedded ram block can be con gured as: ? 1-512 x 18 (quad-port, two read/two write) with optional built in arbitration. ? 1-256 x 36 (dual-port, one read/one write). ? 1-1k x 9 (dual-port, one read/one write). ? 2-512 x 9 (dual-port, one read/one write for each). ? 2 rams with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). ? supports joining of ram blocks. ? two 16 x 8-bit content addressable memory (cam) support. ? fifo 512 x 18, 256 x 36, 1k x 9 or dual 512 x 9. ? constant multiply (8 x 16 or 16 x 8). ? dual-variable multiply (8 x 8). embedded 32-bit internal system bus plus 4-bit par- ity interconnects fpga logic, microprocessor inter- f ace (mpi), embedded ram blocks, and embedded standard cell blocks with 100 mhz bus performance. included are built-in system registers that act as the control and status center for the device. built-in testability: ? full boundary scan ( ieee ? 1149.1 and draft 1149.2 joint test access group (jtag)). ? programming and readback through boundary scan port compliant to ieee draft 1532:d1.7. ? ts_all testability function to 3-state all i/o pins. ? new temperature-sensing diode. new cycle stealing capability allows a typical 15% to 40% internal speed improvement after nal place and route. this feature also enables compliance with many setup/hold and clock-to-out i/o speci cations, and may provide reduced ground bounce for output b uses by allowing e xible delays of switching output b uffers.
lattice semiconductor 3 product brief january 15, 2002 field-programmable gate arrays orca series 4 system features pci local bus compliant. improved powerpc ? /powerquicc mpc 860 and po w erpc ii mpc8260 high-speed synchronous microprocessor interface can be used for con gura- tion, readback, device control, and device status, as w ell as for a general-purpose interface to the fpga logic, rams, and embedded standard cell blocks. glueless interface to synchronous po w erpc proces- sors with user-con gurable address space is pro- vided. new embedded amba ? speci cation 2.0 ahb sys- tem bus ( arm ? processor) facilitates communica- tion among the microprocessor interface, con guration logic, embedded block ram, fpga logic, and embedded standard cell blocks. new network plls meet itu-t g.811 speci cations and provide clock conditioning for ds-1/e-1 and sts-3/stm-1 applications. va r iable size bused readback of con guration data capability with the built-in microprocessor interface and system bus. internal, 3-state, bidirectional buses with simple con- trol provided by the slic. new clock routing structures for global and local clocking signi cantly increases speed and reduces skew (<200 ps for or4e4). new local clock routing structures allow creation of localized clock trees. tw o new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved setup/hold and clock-to-out performance. new double-data rate (ddr) and zero-bus turn- around (zbt) memory interfaces support the latest high-speed memory interfaces. new 2x/4x uplink and downlink i/o capabilities inter- f ace high-speed external i/os to reduced speed internal logic. meets universal test and operations phy interface f or atm (utopia) levels 1, 2, and 3. also meets proposed speci cations for utopia level 4, pos- phy level 3 (2.5 gbits/s), and pos-phy 4 (10 gbits/s) interface standards for packet-over- sonet as de ned by the saturn group. orca foundry development system software s upported by industry-standard cae tools for design entry, synthesis, simulation, and timing analysis.
4 lattice semiconductor product brief january 15, 2002 field-programmable gate arrays orca series 4 system features (continued) 5-7536(f).a figure 1. series 4 fpga block diagram embedded system bus pic plc microprocessor interface (mpi) pfu slic fpga/system bus interface plls embedded block ram high-speed i/os clock pins pio replaced by embedded ip core for fpscs (all 4 sides) (all 4 corners)
lattice semiconductor 5 product brief january 15, 2002 field-programmable gate arrays orca series 4 ordering information 5-6435 (f).l or4exx, ?1 speed grade, 680-pin plastic ball grid array multilayer (pbgam) ta b le 2. device type options ta b le 3. temperature options note: device junction temperature of ?40 ? c to +125 ? c are recommended. ta b le 4. package options tab le 5. orca or4exx series package matrix (speed grade) device voltage or4exx 1.5 v internal 3.3 v/2.5 v/1.8 v/1.5 v i/o symbol description ambient temperature (blank) industrial ?40 ? c to +85 ? c symbol description ba plastic ball grid array (pbga) bc enhanced ball grid array (ebga) bm plastic ball grid array, multilayer (pbgam) devices 256-pin fsbga(ba) 352-pin pbga(ba) 416-pin pbgam(ba) 432-pin ebga(bc) 680-pin pbgam(bm) or4e2 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 or4e4 ? ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 ?1, ?2, ?3 or4e6 ? ?1, ?2, ?3 ? ?1, ?2, ?3 ?1, ?2, ?3 device type package type or4exx ?1 bm number of pins 680 speed grade temperature range
www.latticesemi.com copyright ? 2002 lattice semiconductor all rights reserved printed in u.s.a. ja n uary 15, 2002 pb02-027ncip (replaces pb01-046ncip) ieee is a registered trademark of the institute of electrical and electronics engineers, inc. po w erpc is a registered trademark of international business machines, inc. amba and arm are trademarks of advanced risc machines limited.
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